This invention relates to a method and apparatus for current steering in a digital-to-analog converter (DAC). Most DACs require a current steering cell in order to provide glitch-free operation at the output. Current steering cells require complementary input signals. Prior art cells generated these input signals by using an input signal of one polarity and passing it through an inverter to generate the complementary signal. Such a prior art steering cell is shown in FIG. 1.
Bias voltages bv.sub.1 and bv.sub.2 are fed to bias voltage input terminals 201 and 202, respectively. Representative bias voltages may be 2.0 v and 1.5 v, respectively, for a supply voltage of 3.3 v. Transistors 203 and 204 are the cascode current source transistors for the current steering cell. Cascode transistors 203 and 204 set the biases necessary to establish the current I through the cell. They are of the same polarity type (P-channel in the example), and also are of the same polarity type as the current steering transistors 205 and 206 (which are also P-channel).
Some prior art current steering circuits use a single transistor instead of two transistors 203 and 204, but the cascoded pair of transmitters shown in FIG. 1 provides a higher output impedance. Ideal current sources have infinite output impedance.
Logic cell 207 provides the input signal to line 208, which is coupled to the respective gates of P-channel current steering transistors 205 and 206. Line 208 is coupled directly to the gate of transistor 205, and is coupled through inverter 209 to the gate of transistor 206. As discussed above, inverter 209 ensures that steering transistors 205 and 206 will receive complementary inputs.
The complementary input signals to P-channel steering transistors 205 and 206 cause disturbance of the common mode signal at node 210, which in turn causes disturbance in the value of the cell current I appearing at terminal 211.